/* verilator lint_off DECLFILENAME */
/* verilator lint_off UNUSEDSIGNAL */
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off BLKSEQ */
/* verilator timing_on */
`timescale 1ns/1ps
module dut(input logic clk, input logic a, input logic b);
  logic c;
  always_ff @(posedge clk)
    c <= b;

    a1: assert #0 (!(a & c)) $display("Pass"); else $display("Fail");
    a2: assert final (!(a & c)) $display("Pass"); else $display("Fail");

endmodule

program tb(input logic clk, output logic a, output logic b);
  default clocking m @(posedge clk);
  default input #0;
  default output #0;
  output a;
  output b;
  endclocking
  initial begin
    a = 1;
    b = 0;
    ##10;
    b = 1;
    ##1;
    a = 0;
  end
endprogram
module sva_svtb;
  reg  clk;
  logic a, b;
//...
  dut dut (.*);
  tb tb (.*);
   reg [31:0] seed;
   
   initial begin
      clk = 1;
      seed = 2;
      
      //forever #10 clk = ~clk;
   end
//   always #5 clk = ~clk;
   
   initial begin
      $dumpfile("out.vcd");


      repeat(8)begin
	 clk = ~clk;
	 a = $random();
	 b = $random();
	 
	 $display("a=%h b=%h time %0t clk=%h", a, b, $time, clk);
      end
      $finish();
      $dumpvars(1, sva_svtb);
   end

endmodule
